Designing a Mixed-Signal Audio PCB (also my first PCB!)

The challenge of designing a Printed Circuit Board (PCB) that successfully integrates high-speed digital logic, low-noise analog sensing, and high-current power amplification is a classic exercise in constraint management. This week-long project required precisely this: combining a Digilent Cmod A7 FPGA, sensitive I2S PDM microphones, and a TPA3116 Class D amplifier on a single 4-layer board. Here I detail the progression of design decisions, focusing on the technical rationale behind managing the inherent conflicts between these electrical domains.

The system's primary power source is a 24V DC rail dedicated to the high-power amplifier. The remaining circuitry requires stable, low-voltage rails (5V, 3.3V, 1.8V). The initial design challenge was the efficient and noise-isolated conversion from 24V to these lower voltages.

Balancing Efficiency and Noise

The initial step, converting 24V to a 5V intermediate bus, mandated the use of a Buck Converter. A linear regulator (LDO) was ruled out due to the excessive power dissipation required for the voltage drop, which would have rendered the design thermally unstable. While the buck converter provides high efficiency, it introduces switching ripple into the 5V bus.

This 5V rail is therefore treated as a "dirty" intermediate source, suitable only as an input to subsequent, noise-filtering stages.

Active Noise Filtering for Sensitive Rails

The critical step for noise mitigation involved the strategic deployment of LDOs, particularly those with a high **Power Supply Rejection Ratio (PSRR)**.

The system's power tree was structured as follows:

1. Digital Core (3.3V): A standard LDO converts 5V $\rightarrow$ 3.3V for the FPGA and general logic. FPGAs are robust but also significant sources of high-frequency noise.
2. Analog Sensing (1.8V): A High-PSRR LDO converts 5V $\rightarrow$ 1.8V, placed in close proximity to the T5848 microphones.

The choice of a High-PSRR LDO for the microphone supply is non-negotiable. These devices act as active filters, effectively isolating the sensitive 1.8V rail from the upstream 5V switching ripple and the localized digital noise generated by the FPGA's I/O switching. This isolation is essential, as even minor voltage fluctuations on the microphone supply can be transduced into audible noise.

The decision regarding the ground plane architecture is perhaps the most fundamental in mixed-signal design. I chose to implement a single, continuous ground plane on Layer 2 of the 4-layer stackup, rejecting the traditional split-plane approach.

The Flaw in Split Ground Planes

The conventional wisdom of splitting the ground into AGND and DGND and connecting them with a 0Ω resistor or ferrite bead is often counterproductive in modern high-speed systems. High-speed digital signals, such as the I2S clock, return to their source via the path of least *inductance*, which is the ground plane directly beneath the signal trace.

If a digital trace crosses a physical gap in a split ground plane, the return current is forced to divert around the gap to the nearest connection point (the 0Ω resistor). This detour significantly increases the loop area of the signal path. According to electromagnetic theory, a larger loop area acts as a more efficient loop antenna, radiating noise (EMI) and compromising signal integrity.

Component Partitioning on a Solid Plane

My strategy relied on component partitioning and strict routing discipline:

1. Physical Zoning: The board layout was divided into distinct zones for digital, analog, and power components.
2. Controlled Return Paths: All high-speed digital traces were routed exclusively over the digital zone of the solid ground plane. This ensures that the return current remains localized beneath the trace, minimizing the loop area and preventing digital noise from coupling into the analog region.

Isolating High-Current Returns: Star Grounding

While the digital and analog grounds were unified, the high-current return path of the Class D amplifier required isolation. The amplifier's pulsed current draw (up to 15A peak) can induce transient voltage drops across the ground plane impedance, momentarily "lifting" the ground reference for the entire board—a phenomenon that manifests as a ground loop or hum.

To prevent this, a form of star grounding was implemented: the high-current amplifier ground trace and the low-current digital ground trace were kept physically separate and converged only at a single, designated reference point near the 24V input. This isolates the sensitive digital ground reference from the high-current return noise.

The project's most significant signal integrity challenge was the requirement to transmit the I2S protocol over a distance of up to 15 meters to the remote microphones. I2S is a local bus protocol, and its single-ended signals are highly susceptible to degradation from cable capacitance and noise over long distances.

The Necessity of Differential Signaling

To achieve reliable data transmission, the I2S signals were converted to a robust, noise-immune format: RS-422 Differential Signaling.

1. Conversion and Medium: An RS-422 transceiver was used to convert the single-ended I2S signals (BCLK, LRCLK, DATA) into balanced differential pairs. These pairs were then routed over the twisted-pair wiring of a standard Cat5 Ethernet cable via an RJ45 connector. Differential signaling inherently rejects common-mode noise, as the receiver only evaluates the voltage difference between the two lines.
2. Series Termination: To mitigate signal reflections (ringing) on the high-speed I2S lines, Series Termination Resistors (22Ω to 33Ω) were placed immediately at the FPGA output pins. This matches the trace impedance and ensures a clean signal launch.
3. End-of-Line Termination: Crucially, a 120Ω termination resistor was placed across the differential pair's A and B lines at the receiving end (the microphone breakout). This resistor matches the characteristic impedance of the twisted-pair cable, absorbing the signal energy and preventing reflections that would otherwise corrupt the data.

This complex signal chain—incorporating series termination, level shifting, differential conversion, and end-of-line termination—was essential to guarantee the integrity of the audio data over the extended cable length.

The final phase involved managing the physical constraints of high-power operation and navigating the practicalities of the PCB design toolchain.

High-Current and Thermal Design

The TPA3116 Class D amplifier requires rigorous thermal management. The design incorporated two key features:

1. High-Current Traces: The 24V power and high-current ground traces were specified for 2oz copper and designed with a minimum width of 10mm. This dimension was calculated to maintain a temperature rise well within acceptable limits for the peak 15A current draw.
2. Thermal Vias: The amplifier's central thermal pad was connected to the solid ground plane via a dense array of thermal vias (e.g., a 4x4 grid). This effectively utilizes the entire ground plane as a heatsink, maximizing the thermal dissipation area and ensuring the amplifier operates within its safe temperature range.

Input protection was also implemented as a critical safety measure: $\text{Fuse} \rightarrow \text{TVS Diode} \rightarrow \text{Schottky Diode}$. The Schottky Diode provides essential reverse polarity protection, ensuring that an incorrect power connection results in a fuse failure rather than catastrophic damage to the sensitive digital components.

Non-Trivial Toolchain Challenges

The project encountered several non-trivial challenges related to the KiCad toolchain, particularly when integrating custom components:

1. Footprint Pin Mismatch: Integrating the Cmod A7 module, which uses two 24-pin headers, required careful synchronization between the 48-pin schematic symbol and the physical footprint. A mismatch resulted in numerous Design Rule Check (DRC) errors, highlighting the necessity of ensuring a precise one-to-one mapping between the symbol's pin count and the footprint's pad count.
2. Mechanical Pad Conflicts: A standard header footprint triggered a DRC error (`pad MP not found`). This was caused by a mechanical mounting pad (`MP`) on the footprint that lacked a corresponding electrical pin on the schematic symbol. The resolution required editing the footprint to designate the `MP` pad as a non-numbered, mechanical-only feature, thereby resolving the electrical DRC conflict.
3. Version Control and Portability: The use of custom, imported footprints led to a version control issue where the physical layout data was not tracked by Git. The solution involved migrating these footprints from local Global Libraries to a Project-Specific Library and, critically, modifying the project's `.gitignore` file to ensure the necessary `*.kicad_mod` files were committed to the repository. This step was vital for ensuring the project's portability and collaborative integrity.

The successful design of this mixed-signal audio platform was a function of managing the inherent conflicts between high-speed digital, low-noise analog, and high-current power domains. The project demonstrated the practical application of advanced PCB design principles: hierarchical power management for noise isolation, controlled return paths on a solid ground plane for signal integrity, and the use of differential signaling for robust long-distance communication. The challenges encountered, particularly in the realm of thermal design and toolchain management, underscore the comprehensive skill set required for modern electronic system integration.

1. Power Supply Rejection Ratio (PSRR) in LDOs: *A measure of the regulator's ability to suppress variations in the input voltage from appearing on the output voltage.*

1. Ground Plane Splitting in Mixed-Signal PCBs: *A discussion on the trade-offs between split and unified ground planes, emphasizing the importance of minimizing loop area in high-speed designs.*

1. Series Termination for Signal Integrity: *Application of series resistors to match trace impedance and mitigate signal reflections (ringing) in high-speed digital interfaces.*

1. RS-422 Standard for Differential Signaling: *Technical specification for balanced voltage digital interface circuits, commonly used for noise-immune, long-distance data transmission.*